View CM3202_1188151.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

PRELIMINARY CM3202 DDR VDDQ and Termination Voltage Regulator
Features
* Two linear regulators -Maximum 2A current from VDDQ -Source and sink up to 2A VTT current 1.7V to 2.8V adjustable VDDQ output voltage 500mV typical VDDQ dropout voltage at 2A VTT tracking at 50% of VDDQ Excellent load and line regulation, low noise Fast transient response Meet JEDEC DDR-I and DDR-II memory power spec. Linear regulator design requires no inductors and has low external component count Integrated power MOSFETs Dual purpose ADJ/Shutdown pin Built-in over-current limit with short-circuit foldback and thermal shutdown for VDDQ and VTT Fast transient response 5mA quiescent current TDFN-8 and SOIC-8 packages for high performance thermal dissipation and easy PC board layout Optional RoHS Compliant Lead-free packaging
Product Description
The CM3202 is a dual-output low noise linear regulator designed to meet SSTL-2 and SSTL-3 specifications for DDR-SDRAM VDDQ supply and termination voltage VTT supply. With integrated power MOSFET's, the CM3202 can source up to 2A of VDDQ current, and source or sink up to 2A VTT current. The typical dropout voltage for VDDQ is 500 mV at 2A load current.
* * * * * * * * * * * * * *
The CM3202 provides fast response to transient load changes. Load regulation is excellent, less than 1%, from no load to full load. It also has built-in over-current limits and thermal shutdown at 170C. The CM3202 is packaged in an easy-to-use TDFN-8 and SOIC-8. Low thermal resistance (55C/W) allows it to withstand 1.55W (1) dissipation at 85C ambient. It can operate over the industrial ambient temperature range of -40C to 85C.
Note(1) : If TDFN-8 is mounted on a double-sided printed circuit board with two square inches of copper area, it can to withstand 2W dissipation at 85C ambient then.
Applications
* * * * * * * * DDR memory and active termination buses Desktop Computers, Servers Residential and Enterprise Gateways DSL Modems Routers and Switchers DVD recorders 3D AGP cards LCD TV and STB
Typical Application
3.3V
220u
4.7u 220u 4.7u
VDDQ
VDDQ
1 2 3 4 4.7u
VIN VIN VTT GND
VDDQ VDDQ
8 7 887 6 5 S/D VTT 845
C hip S et
DL0 RT0 DLn RTn
CM3202
ADJSD GND
220u
REF Memory
DDR
1.25V , 2.5A
1k VREF 1u
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
1
PRELIMINARY CM3202
Package Pinout
PACKAGE / PINOUT DIAGRAM
TOP VIEW
8765
TOP VIEW
VDDQ VDDQ ADJSD GND
1234
Pin 1 Marking
VIN VIN VTT GND
1 2 3 4
8 7 6 5
VIN NC VTT NC
1 2 3 4 GND PAD
8 7 6 5
VDDQ ADJSD GND GND
8-Lead SOIC Package CM3202-00DE
Note: This drawing is not to scale.
8-Lead TDFN Package CM3202-00SM
Ordering Information
PART NUMBERING INFORMATION
Lead-free Finish Pins 8 8 Package TDFN SOIC Ordering Part Number1 CM3202-00DE CM3202-00SM Part Marking CM3202 CM3202
Note 1: Parts are shipped in Tape & Reel form unless otherwise specified.
Specifications
ABSOLUTE MAXIMUM RATINGS
PARAMETER VIN to GND Pin Voltages VDDQ ,VTT to GND ADJSD to GND Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering, 10s) RATING [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 [GND - 0.3] to +6.0 -65 to +150 -40 to +85 300 UNITS V V V C C C
(c) 2006 California Micro Devices Corp. All rights reserved.
2
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
05/08/06
PRELIMINARY CM3202
Specifications (cont'd)
ELECTRICAL OPERATING CHARACTERISTICS (SEE NOTE 1)
VIN = 3.3V, typical values are at TA = 25C (unless otherwise specified) SYMBOL VIN VIN VUVLO IQ Supply Voltage Range Under-voltage Lockout UVLO Hysterisis Quiescent Current All outputs are no load VDDQ = 0V, VTT = 0V, ADJSD = 3.3V (shutdown) VDDQ = 2.5V, VTT = 1.25V, (no load) VOUT = 2.5V 1.235 VADJSD = VREF IO = 10mA to 2A VIN = 3.15V to 3.5V, IO = 10mA VIN = 3.15V, IO = 2A VOUT = 1.25V VOUT = 1.25V IO = 0A to 2A IO = 0A to -2A Over Temperature Protection Thermal Shutdown Temperature Thermal Shutdown Hysteresis 3 3.3 2.5 200 200 5 2.8 1.250 30 1 1 500 2.8 2.8 1 1 170 50 1.265 200 3.6 V V mV mA mA A V nA % % mV A A % % C C PARAMETER CONDITIONS MIN TYP MAX UNIT S
VDDQ Regulator Output Current Limit VREF IBIAS VR LOAD VR LINE VDROPOUT VTT Regulator Output Current Limit (Source) Output Current Limit (Sink) VR VTTLOAD Load Regulation Reference Voltage Input Bias Current (IADJ) Load Regulation Line Regulation Dropout Voltage
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
3
PRELIMINARY CM3202
Typical Operating Characteristics
VTT vs. VDDQ
1.65 1.55 1.45
VDDQ vs. Temperature
2.51 2.505
VTT (V)
1.35
VDDQ (V)
1.25 1.15 1.05 0.95 0.85 0.75 1.5 1.75 2 2.25 2.5 2.75 3 3.25
2. 5 2.495 2.49 -40 -20 0 20 40 60 80
o
VDDQ (V)
Temperatur e
10 0
12 0
14 0
C
VDDQ vs. Load Current
VDDQ Dropout vs. IDDQ
Dropout Voltage (mV)
VDDQ (V)
Ta=25 oC
Ta=25 oC Vin=3.3V
IDDQ (A)
IDDQ (A)
Startup into Full Load
Vin UVLO
VDDQ
VTT 1V/div 1ms/div
(c) 2006 California Micro Devices Corp. All rights reserved.
4
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
05/08/06
PRELIMINARY CM3202
Typical Operating Characteristics
VDDQ Transient Response
(cont'd)
VTT Transient Response
IOUT VDDQ
IOUT VTT
VIN = 3.3V IOUT Step: 15mA ~ 1.5A
VIN = 3.3V IOUT Step: -750mA ~ +750mA
With TDFN-8 Package
VDDQ Transient Response
VTT Transient Response
IOUT VDDQ
IOUT VTT
VIN = 3.3V IOUT Step: 15mA ~ 700mA
VIN = 3.3V IOUT Step: -350mA ~ +350mA
With SOIC-8 Package
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
5
PRELIMINARY CM3202
Pin Description Pin Descriptions
PIN DESCRIPTIONS
PIN(S) TDFN 8 PIN(S) SOIC 8 NAME DESCRIPTION
1 2, 4 3 5, 6
1, 2 3 4, 5
VIN NC VTT GND
Input voltage pin, typically 3.3V from the silver box. VTT regulator output voltage pin, which is preset to 50% of VDDQ. Ground pin. The back tab is also ground and serves as the package heatsink. It should be soldered to the circuit board copper to remove excess heat from the IC. This pin is for VDDQ output voltage Adjustment. The VDDQ output voltage is set using an external resistor divider connected to ADJSD. The output voltage is determined by the following formula
R1 + R2 V DDQ = 1.25V x -------------------R1
7
6
ADJSD
where R1 is the ground-side resistor and R2 is the upper resistor of the divider. Connect these resistors to the VDDQ output at the point of regulation. In addition, functions as a Shutdown pin. Apply a voltage higher than VIN0.6V to this pin to simultaneously shutdown both VDDQ and VTT outputs. The outputs are restored when the voltage is lowered below VIN-0.6V. A low-leakage diode in series with the Shutdown signal is recommended to avoid interference with the voltage adjustment setting.
8
7, 8
VDDQ
VDDQ regulator output voltage pin.
(c) 2006 California Micro Devices Corp. All rights reserved.
6
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
05/08/06
PRELIMINARY CM3202
Application Information (cont'd)
1.22V
CM3202
Application Information
Powering DDR Memory Double-Data-Rate (DDR) memory has provided a huge step in performance for personal computers, servers and graphic systems. As is apparent in its name, DDR operates at double the data rate of earlier RAM, with two memory accesses per cycle versus one. DDR SDRAM's transmit data at both the rising falling edges of the memory bus clock. DDR's use of Stub Series Terminated Logic (SSTL) topology improves noise immunity and power-supply rejection, while reducing power dissipation. To achieve this performance improvement, DDR requires more complex power management architecture than previous RAM technology. Unlike the conventional DRAM technology, DDR SDRAM uses differential inputs and a reference voltage for all interface signals. This increases the data bus bandwidth, and lowers the system power consumption. Power consumption is reduced by lower operating voltage, a lower signal voltage swing associated with Stub Series Terminated Logic (SSTL_2) and by the use of a termination voltage, VTT. SSTL_2 is an
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
industry standard, defined in JEDEC document JESD8-9. SSTL_2 maintains high-speed data bus signal integrity by reducing transmission reflections. JEDEC further defines the DDR SDRAM specification in JESD79C. DDR memory requires three tightly regulated voltages: VDDQ, VTT, and VREF (see Figure 1). In a typical SSTL_2 receiver, the higher current VDDQ supply voltage is normally 2.5V with a tolerance of 200-mV. The active bus termination voltage, VTT, is half of VDDQ. VREF is a reference voltage that tracks half of VDDQ, 1%, and is compared with the VTT terminated signal at the receiver. VTT must be within 40-mV of VREF.
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
7
PRELIMINARY CM3202
Application Info (cont'd)
VDDQ VTT (=VDDQ/2)
Rt = 25 Rs = 25
VDDQ
Line Receiver VREF (=VDDQ/2)
Transmitter
Figure 1. Typical DDR terminations, Class II The VTT power requirement is proportional to the number of data lines and the resistance of the termination resistor, but does not vary with memory size. In a typical DDR data bus system each data line termination may momentarily consume 16.2-mA to achieve the 405-mV minimum over VTT needed at the receiver:
405mVI terminaton = --------------------- = 16.2mA Rt ( 25 )
and the two-quadrant VTT termination regulator has current sink and source capability to 2A. The VDDQ linear regulator uses a PMOS pass element for a very low dropout voltage, typically 500mV at a 2A output. The output voltage of VDDQ can be set by an external voltage divider. The second output, VTT, is regulated at VDDQ/2 by an internal resistor divider. The VTT regulator can source, as well as sink, up to 2A current. The CM3202 is designed for optimal operation from a nominal 3.3VDC bus, but can work with VIN as high as 5V. When operating at higher VIN voltages, attention must be given to the increased package power dissipation and proportionally increased heat generation. VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate VREF can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small ceramic bypass capacitor can also be added for improved noise performance. Input and Output Capacitors The CM3202 requires that at least a 220F electrolytic capacitor be located near the VIN pin for stability and to maintain the input bus voltage during load transients. An additional 4.7F ceramic capacitor between the VIN and the GND, located as close as possible to those pins, is recommended to ensure stability. A minimum of a 220F electrolytic capacitor is recommended for the VDDQ output. An additional 4.7F ceramic capacitor between the VDDQ and GND, located very close to those pins, is recommended. A minimum of a 220F, electrolytic capacitor is recommended for the VTT output. This capacitor should have low ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and thus are a good choice. In addition, place a 4.7F ceramic capacitor between the VTT pin and GND, located very close to those pins. The total ESR must be low enough to keep the transient within the VTT window of 40mV during the transition for source to sink. An average current step of 0.5A requires:
40mV ESR < -------------- = 40m 1A
A typical 64 Mbyte SSTL-2 memory system, with 128 terminated lines, has a worst-case maximum VTT supply current up to 2.07A. However, a DDR memory system is dynamic, and the theoretical peak currents only occur for short durations, if they ever occur at all. These high current peaks can be handled by the VTT external capacitor. In a real memory system, the continuous average VTT current level in normal operation is less than 200 mA. The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to controllers and other circuitry. The current level typically stays within a range of 0.5A to 1A, with peaks up to 2A or more, depending on memory size and the computing operations being performed. The tight tracking requirements and the need for VTT to sink, as well as source, current provide unique challenges for powering DDR SDRAM.
CM3202 Regulator The CM3202 dual output linear regulator provides all of the power requirements of DDR memory by combining two linear regulators into a single TDFN-8 or SOIC-8 package. VDDQ regulator can supply up to 2A current,
(c) 2006 California Micro Devices Corp. All rights reserved.
Both outputs will remain stable and in regulation even during light or no load conditions.
8
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
05/08/06
PRELIMINARY CM3202
Application Info (cont'd) Thermal Considerations
Adjusting VDDQ Output Voltage The CM3202 internal bandgap reference is set at 1.25V. The VDDQ voltage is adjustable by using a resistor divider, R1 and R2:
R1 + R2 V DDQ = V ADJ x -------------------R1
Typical Thermal Characteristics The overall junction to ambient thermal resistance (JA) for device power dissipation (PD) primarily consists of two paths in the series. The first path is the junction to the case (JC) which is defined by the package style and the second path is case to ambient (CA) thermal resistance which is dependent on board layout. The final operating junction temperature for any condition can be estimated by the following thermal equation:
T JUNC = T AMB + P D x ( JC ) + P D x ( CA ) = T AMB + P D x ( CA )
where VADJ = 1.25V (-1%). For best regulator stability, we recommend that R1 and R2 not exceed 10k each. Shutdown ADJSD also serves as a shutdown pin. When this is pulled high, > (VIN - 0.6V), the VDDQ output is turned off and both source and sink MOSFET's of the VTT regulator are set to a high impedance state. During shutdown, the quiescent current is reduced to less than 3mA, independent of output load. It is recommended that a 1N914 or equivalent low leakage diode be placed between ADJSD Pin and an external shutdown signal to prevent interference with the ADJ pin's normal operation. When the diode anode is pulled low, or left open, the CM3202 is again enabled. Current Limit, Foldback and Over-temperature Protection The CM3202 features internal current limiting with thermal protection. During normal operation, VDDQ limits the output current to approximately 2A and VTT limits the output current to approximately 2A. When VTT is current limiting into a hard short circuit, the output current folds back to a lower level, about 1A, until the overcurrent condition ends. While current limiting is designed to prevent gross device failure, care should be taken not to exceed the power dissipation ratings of the package. If the junction temperature of the device exceeds 170-C (typical), the thermal protection circuitry triggers and shuts down both outputs. Once the junction temperature has cooled to below about 120-C, the CM3202 returns to normal operation.
When a CM3202 is mounted on a double-sided printed circuit board with two square inches of copper allocated for "heat spreading," the JA is approximately 42.5-C/Watt for the CM3202-00DE (TDFN-8) and 85-C/Watt for CM3202-00SM (SOIC-8). Based on the over temperature limit of 170C with an ambient of 85C, the available power of the package will be:
PD(TDFN8) =
170 C 85C = 2W 42.5 C / W
PD(SOIC8) =
170 C 85C = 1W 85C / W
PCB Layout Considerations TheCM3202 has a heat spreader attached to the bottom of the TDFN-8 package in order for the heat to be transferred more easily from the package to the PCB. The heat spreader is a copper pad of dimensions just smaller than the package itself. By positioning the matching pad on the PCB top layer to connect to the spreader during the manufacturing, the heat will be transferred between the two pads. See the Figure 2, the CM3202-00DE (TDFN-8) and CM3202-00SM (SOIC-8) show the recommended PCB layout. Please be noted that there are six vias in the SOIC-8 package (four vias in the TDFN-8 package) on either side to allow the heat to dissipate into the ground and power planes on the inner layers of the PCB. Vias can be placed underneath the chip, but this can be resulted in
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
9
PRELIMINARY CM3202
Application Info (cont'd)
blocking of the solder. The ground and power planes need to be at least 2 square inches of copper by the vias. It also helps dissipation if the chip is positioned away from the edge of the PCB, and not near other heat-dissipating devices. A good thermal link from the PCB pad to the rest of the PCB will assure the best
Bottom Layer Ground Plane
heat transfer from the CM3202-00DE (TDFN-8) to ambient, JA, of approximately 42.5 -C/W, or JA of approximately 85 C/W for the CM3202-00SM (SOIC8).
Top View
Top Layer Copper Connects to Heat Spreader
Pin Solder Mask
Thermal PAD Solder Mask Vias (0.3mm Diameter)
(TDFN-8 Package) Top View
Bottom Layer Ground Plane Top Layer Copper Connects to Heat Spreader
Pin Solder Mask
Vias (0.3mm Diameter)
(SOIC-8 Package)
Note: This drawing is not to scale
Figure 2. Thermal Layout
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
10
PRELIMINARY CM3202
Mechanical Details
TDFN-08 Mechanical Specifications The CM3202-00DE is supplied in an 8-lead, 0.65mm pitch TDFN package. Dimensions are presented below. Mechanical Package Diagrams
D
PACKAGE DIMENSIONS
Package JEDEC No. Leads Dim. A A1 A2 A3 b D D2 E E2 e K L # per tape and reel 0.20 0.20 0.30 0.45 1.60 1.90 0.25 Millimeters Min 0.70 0.00 0.45 Nom 0.75 0.02 0.55 0.20 0.30 3.00 2.00 3.00 1.70 0.65 0.008 0.008 0.012 0.018 3000 pieces 1.80 0.063 2.10 0.075 0.35 0.010 Max 0.80 0.05 0.65 Min 0.028 0.000 0.018 TDFN MO-229 (Var. WEEC-1)= 6 Inches Nom 0.030 0.001 0.022 0.008 0.012 0.118 0.079 0.118 0.067 0.026 0.071
0.08 C
8
7
6
5
E
Max 0.031 0.002 0.026 0.014 0.083
0.10 C
Pin 1 Marking
1
2
3
4
TOP VIEW
A1
SIDE VIEW
A
A3 A2
5
Controlling dimension: millimeters
6
D2
7
8
= This package is compliant with JEDEC standard MO-229, variation VEEC-1 with exception of the "D2", "E2" and "b" dimensions as called out in the table above.
E2
C0.25 GND PAD L
K e
4
3
2
1
b
8X
BOTTOM VIEW
0.10
M
CAB
Package Dimensions for 8-Lead TDFN
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
11
PRELIMINARY CM3202
Mechanical Details (cont'd)
SOIC-8 Mechanical Specifications Dimensions for CM3202-00SM devices packaged in 8lead SOIC packages with an intagrated heatslug are presented below. Mechanical Package Diagrams TOP VIEW
PACKAGE DIMENSIONS
Package Leads Dimensions A A1 B C D E e H L # per tube # per tape and reel Millimeters Min 1.30 0.03 0.33 0.18 4.83 3.81 5.79 0.41 Max 1.62 0.10 0.51 0.25 5.00 3.99 6.20 1.27 Min 0.051 0.001 0.013 0.007 0.190 0.150 0.228 0.016 SOIC-8 8 Inches Max 0.064 0.004 0.020 0.010 0.197 0.157
D
8 7 6 5
H
Pin 1 Marking
E
1
2
3
4
SIDE VIEW
A
SEATING PLANE
1.27 BSC
0.050 BSC 0.244 0.050
A1 B e
100 pieces* 2500 pieces Controlling dimension: inches
END VIEW
C
* This is an approximate number which may vary.
L
** Centered on package centerline. Package Dimensions for SOIC-8
(c) 2006 California Micro Devices Corp. All rights reserved. 05/08/06
490 N. McCarthy Blvd., Milpitas, CA 95035-5112
l
Tel: 408.263.3214
l
Fax: 408.263.7846
l
www.cmd.com
12

▲Up To Search▲

Price & Availability of CM3202

	To Download CM3202 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .